A dynamic random access memory (DRAM) device consists of an arrangement of individual memory cells. Each memory cell comprises a capacitor capable of holding a charge and a field effect transistor, hereinafter referred to as an access transistor, for accessing the capacitor charge. The charge is referred to as a data bit and can be either a high voltage or a low voltage. Therefore, the memory has two states; often thought of as the true logic state and the complementary logic state. There are two options available in a DRAM memory: a bit of data may be stored in a specific cell in the write mode, or a bit of data may be retrieved from a specific cell in the read mode. The data is transmitted on signal lines, also called digit lines, which are coupled to Input/Output lines through field effect transistors used as switching devices. The switching devices are called decode transistors. For each bit of data stored, its true logic state is available at an I/O line and its complementary logic state is available at a line designated I/O*. Thus each cell has two digit lines, digit and digit*, corresponding to I/O and I/O* respectively. For purposes of this discussion, I/O and I/O* lines are often referred to as just I/O lines.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array comprises a configuration of intersecting rows and columns and a memory cell is associated with each intersection. In order to read from or write to a cell, the particular cell in question must be selected, also called addressed. The address for the selected cell is represented by input signals to a row decoder and to a column decoder. The row decoder activates a wordline in response to the row address. The selected wordline activates the access transistor for each of the memory cells in electrical communication with the selected wordline. Next the column decoder activates a column decoder output in response to the column address. The active column decoder output selects the desired digit line pair. For a read operation the selected wordline activates the access transistors for a given row address, and data is latched to the digit line pairs. The column decoder output selects and activates the decode transistors such that the data is transferred from the selected digit line pair to the I/O lines.
U.S. Pat. No. 5,175,450 entitled "Apparatus for Providing Multi-Level Potentials at a Sense Node" is herein incorporated by reference to further the readers understanding of a DRAM.
The row decoder comprises decode circuitry for determining which wordline is selected for a desired address and for determining which wordlines are non-selected. The row decoder also comprises driver circuitry for driving the selected and the non-selected wordlines to potentials having active and inactive logic states respectively. The active wordline has a potential capable of activating the access transistors in electrical communication with the active wordline and the inactive wordline has a potential capable of deactivating the access transistors in electrical communication with the non-selected wordlines. For this discussion the potential of a selected wordline is higher than the potential of a non-selected wordline.
Typically the decode circuitry comprises a primary decoder and a secondary decoder for generating a primary select signal, S.sub.1 *, and at least one secondary select signal, S.sub.2, respectively. The asterisk indicates that the signal is active low. The primary and secondary select signals are used as inputs to the driver circuitry of the row decoder. The driver portion typically comprises an inverter portion and a latch portion. The primary select signal is typically inverted to the wordline by the inverter portion, and the secondary select signal regulates the switching of the primary select signal to the inverter portion. The latch portion latches a non-selected wordline to the potential capable of deactuating the access transistor.
Typical decoder circuitries can comprise either MOS decodes utilizing NAND circuitry or NOR circuitry, or tree decode circuitry. FIGS. 1, 2 and 3 are examples of a portion of the NAND, NOR, and tree decode circuitries respectively. The decode circuitries of the row decoder provide predecoded addresses to select the driver portion of the row decoder circuit. MOS decode circuitry provides predecode signals comprising the primary select signal, S.sub.1 *, and the secondary select signal, S.sub.2. Although the specific decode circuitry determining the values of S.sub.1 * and S.sub.2 can vary, the variations are well known in the art. FIGS. 1-3 have been included to provide examples of portions of possible decode circuitries. FIG. 1 is an example of a portion of a CMOS NAND decode circuit wherein each of the secondary select signals, S.sub.2A, S.sub.2B, S.sub.2C and S.sub.2D, is a one of four decode having four phases, and wherein S.sub.1 * (not shown) comes from a one of 64 CMOS NAND decode used to decode 256 wordlines. FIG. 2 is an example of a portion of a CMOS NOR decode circuit wherein each of the primary select signals, S.sub.1A *, S.sub.1B *, S.sub.1C * and S.sub.1D *, is a one of four decode using four phases, and wherein secondary select signal S.sub. 2, (not shown), comes from a one of 64 CMOS NOR decode used to decode 256 wordlines.
In the circuits of FIGS. 1 and 2, the secondary select signal controls the activation of a single pass transistor. The decode circuitry may employ the tree decode configuration wherein a plurality of serially connected pass transistors are activated in order to drive the selected wordline to a high logic level. In the example depicted by FIG. 3 predecode address signals activate three serially connected pass transistors. For example if predetermined address signals RA56(0), RA34(0), and RA12(0) are high and the remaining predecode addresses are low, transistors 1, 2, and 3 are activated providing an electrical path between points 4 and 5. These decode circuitries are well known to those skilled in the art.
FIG. 4 is a simplified schematic of the driver circuit of the related art. Each wordline in the array has a similar driver circuit. In FIG. 4, a MOS decode has been utilized to provide a primary select signal S.sub.1 * at primary select node 4 and a secondary select signal S.sub.2 at secondary select node 6. The select signals S.sub.1 * and S.sub.2 control the potential of the wordline 8. The primary select signal is transmitted through NMOS transistor 9 to an inverter/latch portion 11 when the secondary select signal is high. When select signal S.sub.2 is high, NMOS transistor 9 activates and the select signal S.sub.1 * is inverted to the wordline 8.
FIG. 5 is a simplified schematic of a portion of the decode circuitry of a typical row decoder of the related art. Primary select signals S.sub.1 * and S.sub.1 '* and secondary select signals S.sub.2 and S.sub.2 ' are generated by decode circuitry (not shown). The purpose of this discussion is to provide an understanding of the final mechanism for activating and deactivating the wordlines and to provide an understanding of the relationship between the select signals and the driver circuit. At the onset of each read or write cycle, all of the wordlines are typically reset to a low potential. In this case, select signals S.sub.1 *, S.sub.1 '*, S.sub.2, and S.sub.2 ' have a high potential which take the potentials of the wordlines 12, 14, 16, and 18 low.
During the selection of a wordline the secondary select signals go low except for the secondary select signal which activates the pass transistor in electrical communication with the selected wordline. All of the primary select signals remain high except for the primary select signal which must be inverted to the selected wordline.
Still referring to FIG. 5, assume the desired address selects wordline 14. In this case select signal S.sub.2 goes low and select signal S.sub.2 ' is high; and select signal S.sub.1 '* goes low, and select signals S.sub.1 * is high. The low select signal S.sub.1 '* is inverted to wordline 14 through activated transistor 22. Although transistors 21 and 23 are deactivated the wordlines 12 and 16 remain at the initial low potential due to a latching of the low potential by the inverter/latch portion 11 of the driver circuits. Wordline 18 is driven low when the high potential of S.sub.1 * is driven through activated transistor 24 and inverted to wordline 18.
FIG. 6 is exemplary of driver circuitry 26 of a row decoder circuit of the related art. A non-selected wordline is pulled toward the reference potential through transistor 28 and a selected wordline is pulled toward a high potential of V.sub.cc through transistor 30. Throughout this discussion V.sub.cc refers to a supply potential externally applied to the circuit. One typical value of V.sub.cc is 5 volts.
FIG. 7 is exemplary of further driver circuitry 32 of the related art. Transistor 33 is used during power up of the device to isolate transistor 35's p-type drain from V.sub.cc until V.sub.ccp has reached it full potential. V.sub.ccp is a potential generated internally by pumping the supply potential to a greater value. Typically V.sub.ccp is 1 to 2 volts greater than V.sub.cc. Charge pumps used for generating V.sub.ccp are well known to those skilled in the art and may take several embodiments. There are at least two advantages to using a V.sub.ccp rather than a V.sub.cc. First the device has better write back to a memory cell and secondly the digit lines are pulled to a high logic state faster than when V.sub.cc is used.
In order to conserve power supply potentials of many memory devices have been decreased from the typical 5 volt supply. A low supply voltage of 3.3 volts is increasingly replacing the 5 volt operation. There are disadvantages associated with the lower supply potentials.
Sensing a high logic state on the digit lines becomes more difficult as the value of the supply potential deceases since there is typically a decrease in the potential stored. Sensing the high logic state on the digit line is referred to as "1"s detection.
It is another well known problem in the art that the difference in potential between a wordline and a corresponding digit line can easily cause leakage current thereby sacrificing the integrity of the memory device by allowing the charge stored in the storage capacitor to discharge. Ultimately when the cell is selected the cell may contain erroneous data.
The access devices in the array see a certain minimum digit line potential on a reference digit line of a digit line pair during the majority of the period of one cycle of cell selection. In current applications the digit lines are typically held at the ground reference potential, therefore a V.sub.gs of 0 volts may well allow the access device to conduct leakage current.
When there is an increased rate of charge leakage the cell's "1"s charge is mistaken for a zeros charge and faster refresh cycles are required in order to provide memory preservation thereby increasing power consumption.
The leakage current of a particular DRAM access device can have, given a specific gate to source voltage (V.sub.gs), and still have data retention for a given refresh specification is defined by the equation Leakage=CdV/dt, where C is the capacitance of the storage capacitor, Dv is about half of the operating potential, and dt is the time between refresh cycles. For a typical DRAM cell capacitance, refresh specifications and operating potential, the leakage current must be smaller than or equal to 1 to 2 pico amp for a given V.sub.gs of zero volts.
This region of operation near V.sub.GS =0V and less than the threshold voltage of the device is typically defined as the subthreshold leakage region. This subthreshold leakage (or current), is proportional to the log of Gate-Source voltage in this region. The threshold voltage is the minimum voltage that must be applied between the gate and the source in order that appreciable current flows in the device. A subthreshold characteristic is the response of the access device to the subthreshold potential.
There is a direct correlation between a devices subthreshold characteristics and the amount of drive available when using the device as a digital switch or an analog driver. Low threshold voltage devices, such as those having threshold voltages equal to 0 volts, typically have good drive characteristics, however they typically have high leakage characteristics. Thus, it is difficult to simultaneously acquire good drive and good subthreshold or leakage characteristics.
Although DRAM's are generally manufactured with as few mask steps as possible, often one mask step is added to the manufacturing process to effectively create two different types of devices, one of which has good leakage characteristics and one of which has good drive characteristics. Both types of devices have a similar carrier type. The device with good leakage characteristics is used for access devices in the memory array, and the device with good drive characteristics is used in the peripheral circuitry. In this discussion the peripheral circuitry comprises all circuitry on the memory device other than access devices.